CUDA: fix non-cont. inputs for batched mat mul (#13155)
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7d3af70b08
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cdf76586b2
4 changed files with 94 additions and 42 deletions
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@ -1720,15 +1720,15 @@ static __global__ void k_compute_batched_ptrs(
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size_t nb12, size_t nb13,
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size_t nbd2, size_t nbd3,
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int64_t r2, int64_t r3) {
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int64_t i13 = blockIdx.x * blockDim.x + threadIdx.x;
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int64_t i12 = blockIdx.y * blockDim.y + threadIdx.y;
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const int64_t i13 = blockIdx.x * blockDim.x + threadIdx.x;
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const int64_t i12 = blockIdx.y * blockDim.y + threadIdx.y;
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if (i13 >= ne13 || i12 >= ne12) {
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return;
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}
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int64_t i03 = i13 / r3;
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int64_t i02 = i12 / r2;
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const int64_t i03 = i13 / r3;
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const int64_t i02 = i12 / r2;
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ptrs_src[0*ne23 + i12 + i13*ne12] = (const char *) src0_as_f16 + i02*nb02 + i03*nb03;
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ptrs_src[1*ne23 + i12 + i13*ne12] = (const char *) src1_as_f16 + i12*nb12 + i13*nb13;
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@ -1742,6 +1742,10 @@ static void ggml_cuda_mul_mat_batched_cublas(ggml_backend_cuda_context & ctx, co
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GGML_ASSERT(ggml_backend_buffer_is_cuda(src0->buffer));
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GGML_ASSERT(src0->type == GGML_TYPE_F16);
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// Byte offsets and tensor dimensions are currently used in an inconsistent way for dst.
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// As long as dst is contiguous this does not matter though.
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GGML_ASSERT(ggml_is_contiguous(dst));
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GGML_TENSOR_BINARY_OP_LOCALS
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const int64_t ne_dst = ggml_nelements(dst);
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@ -1750,21 +1754,31 @@ static void ggml_cuda_mul_mat_batched_cublas(ggml_backend_cuda_context & ctx, co
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CUBLAS_CHECK(cublasSetStream(ctx.cublas_handle(), main_stream));
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void * src0_ddq = src0->data;
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half * src0_f16 = (half *) src0_ddq;
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float * src1_ddf = (float *) src1->data;
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float * dst_ddf = (float *) dst->data;
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const half * src0_f16 = (const half *) src0->data;
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float * dst_ddf = (float *) dst->data;
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const half * src1_f16 = (const half *) src1->data;
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const size_t ts_src1 = ggml_type_size(src1->type);
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GGML_ASSERT(nb10 == ts_src1);
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int64_t s11 = nb11 / ts_src1;
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int64_t s12 = nb12 / ts_src1;
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int64_t s13 = nb13 / ts_src1;
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ggml_cuda_pool_alloc<half> src1_f16_alloc(ctx.pool());
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// convert src1 to fp16
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ggml_cuda_pool_alloc<half> src1_f16_alloc(ctx.pool());
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if (src1->type != GGML_TYPE_F16) {
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const to_fp16_cuda_t to_fp16_cuda = ggml_get_to_fp16_cuda(src1->type);
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const to_fp16_nc_cuda_t to_fp16_cuda = ggml_get_to_fp16_nc_cuda(src1->type);
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const int64_t ne_src1 = ggml_nelements(src1);
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src1_f16_alloc.alloc(ne_src1);
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GGML_ASSERT(to_fp16_cuda != nullptr);
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to_fp16_cuda(src1_ddf, src1_f16_alloc.get(), ne_src1, main_stream);
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to_fp16_cuda(src1_f16, src1_f16_alloc.get(), ne10, ne11, ne12, ne13, s11, s12, s13, main_stream);
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src1_f16 = src1_f16_alloc.get();
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s11 = ne10;
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s12 = ne11*s11;
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s13 = ne12*s12;
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}
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half * src1_f16 = src1->type == GGML_TYPE_F16 ? (half *) src1_ddf : src1_f16_alloc.get();
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ggml_cuda_pool_alloc<half> dst_f16(ctx.pool());
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char * dst_t;
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@ -1824,13 +1838,13 @@ static void ggml_cuda_mul_mat_batched_cublas(ggml_backend_cuda_context & ctx, co
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int i02 = i12 / r2;
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CUBLAS_CHECK(
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cublasGemmEx(g_cublas_handles[g_main_device], CUBLAS_OP_T, CUBLAS_OP_N,
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ne01, ne11, ne10,
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alpha, (const char *) src0_as_f16 + i02*src0->nb[2] + i03*src0->nb[3] , CUDA_R_16F, nb01/sizeof(half),
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(const char *) src1_as_f16 + i12*src1->nb[2]/2 + i13*src1->nb[3]/2, CUDA_R_16F, nb11/sizeof(float),
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beta, ( char *) dst_t + i12*nbd2 + i13*nbd3, cu_data_type, ne01,
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cu_compute_type,
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CUBLAS_GEMM_DEFAULT_TENSOR_OP));
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cublasGemmEx(ctx.cublas_handle(), CUBLAS_OP_T, CUBLAS_OP_N,
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ne01, ne11, ne10,
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alpha, (const char *) src0_f16 + i03*nb03 + i02*nb02, CUDA_R_16F, nb01/sizeof(half),
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src1_f16 + i13*s13 + i12*s12, CUDA_R_16F, s11,
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beta, ( char *) dst_t + i13*nbd3 + i12*nbd2, cu_data_type, ne0,
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cu_compute_type,
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CUBLAS_GEMM_DEFAULT_TENSOR_OP));
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}
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}
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}
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@ -1841,15 +1855,15 @@ static void ggml_cuda_mul_mat_batched_cublas(ggml_backend_cuda_context & ctx, co
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CUBLAS_CHECK(
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cublasGemmStridedBatchedEx(ctx.cublas_handle(), CUBLAS_OP_T, CUBLAS_OP_N,
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ne01, ne11, ne10,
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alpha, (const char *) src0_f16, CUDA_R_16F, nb01/nb00, nb02/nb00, // strideA
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(const char *) src1_f16, CUDA_R_16F, nb11/nb10, nb12/nb10, // strideB
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beta, ( char *) dst_t, cu_data_type, ne01, nb2/nb0, // strideC
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alpha, src0_f16, CUDA_R_16F, nb01/nb00, nb02/nb00, // strideA
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src1_f16, CUDA_R_16F, s11, s12, // strideB
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beta, dst_t, cu_data_type, ne0, ne1*ne0, // strideC
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ne12*ne13,
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cu_compute_type,
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CUBLAS_GEMM_DEFAULT_TENSOR_OP));
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} else {
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// use cublasGemmBatchedEx
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const int ne23 = ne12*ne13;
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const int64_t ne23 = ne12*ne13;
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ggml_cuda_pool_alloc<const void *> ptrs_src(ctx.pool(), 2*ne23);
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ggml_cuda_pool_alloc< void *> ptrs_dst(ctx.pool(), 1*ne23);
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@ -1861,8 +1875,8 @@ static void ggml_cuda_mul_mat_batched_cublas(ggml_backend_cuda_context & ctx, co
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ne12, ne13,
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ne23,
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nb02, nb03,
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src1->type == GGML_TYPE_F16 ? nb12 : nb12/2,
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src1->type == GGML_TYPE_F16 ? nb13 : nb13/2,
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src1->type == GGML_TYPE_F16 ? nb12 : s12*sizeof(half),
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src1->type == GGML_TYPE_F16 ? nb13 : s13*sizeof(half),
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nbd2, nbd3,
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r2, r3);
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CUDA_CHECK(cudaGetLastError());
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@ -1871,8 +1885,8 @@ static void ggml_cuda_mul_mat_batched_cublas(ggml_backend_cuda_context & ctx, co
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cublasGemmBatchedEx(ctx.cublas_handle(), CUBLAS_OP_T, CUBLAS_OP_N,
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ne01, ne11, ne10,
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alpha, (const void **) (ptrs_src.get() + 0*ne23), CUDA_R_16F, nb01/nb00,
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(const void **) (ptrs_src.get() + 1*ne23), CUDA_R_16F, nb11/nb10,
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beta, ( void **) (ptrs_dst.get() + 0*ne23), cu_data_type, ne01,
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(const void **) (ptrs_src.get() + 1*ne23), CUDA_R_16F, s11,
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beta, ( void **) (ptrs_dst.get() + 0*ne23), cu_data_type, ne0,
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ne23,
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cu_compute_type,
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CUBLAS_GEMM_DEFAULT_TENSOR_OP));
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@ -1936,7 +1950,7 @@ static void ggml_cuda_mul_mat(ggml_backend_cuda_context & ctx, const ggml_tensor
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} else if (!split && use_mul_mat_vec_q) {
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ggml_cuda_mul_mat_vec_q(ctx, src0, src1, nullptr, dst);
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} else if (!split && src0->type == GGML_TYPE_F16 && (src1->type == GGML_TYPE_F16 || !any_gpus_with_slow_fp16) &&
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dst->op_params[0] == GGML_PREC_DEFAULT && !ggml_is_transposed(src0) && !ggml_is_transposed(src1) && src1->ne[2]*src1->ne[3] > 1) {
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!ggml_is_transposed(src0) && !ggml_is_transposed(src1) && src1->ne[2]*src1->ne[3] > 1) {
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// general KQ + KQV multi-batch without FlashAttention
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ggml_cuda_mul_mat_batched_cublas(ctx, src0, src1, dst);
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} else if (use_mul_mat_vec) {
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